Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time

研究成果: Conference contribution

抄録

A technique to save the frequency of write operation on the non-volatile memory is proposed for reducing dynamic power dissipation of non-volatile logic LSI which shortens its break-even time for power gating. The proposed technique is realized by combining a selective write method with a coding technique. The selective write method compares input words and stored words, and rejects redundant write operation. Moreover, the use of the data coding technique shortens the Hamming distance between adjacent words in an input data sequence and reduces the frequency of bit reversal in the non-volatile memory, which results in the further reduction in the power dissipation due to write operation. Through the design and evaluation of a non-volatile 8-bit counter, it is observed that the proposed technique shortens the break-even time for power gating by up to 85.2% with a small hardware overhead.

本文言語English
ホスト出版物のタイトルProceedings - 2015 IEEE 45th International Symposium on Multiple-Valued Logic, ISMVL 2015
出版社IEEE Computer Society
ページ152-157
ページ数6
ISBN(電子版)9781479917778
DOI
出版ステータスPublished - 2015 9 2
イベント45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015 - Waterloo, Canada
継続期間: 2015 5 182015 5 20

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
2015-September
ISSN(印刷版)0195-623X

Other

Other45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015
CountryCanada
CityWaterloo
Period15/5/1815/5/20

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

フィンガープリント 「Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル