Wafer thinning for high-density three dimensional integration - 12-inch wafer-level 3D-LSI program at GINTI

M. Murugesan, T. Fukushima, J. C. Bea, H. Hashimoto, Y. Sato, K. W. Lee, M. Koyanagi

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Thinning down large scale integrated-chip (LSI) wafers to below 50 μm thickness is inevitable for the wafer-to-wafer (WtW) process as well as chip-to-wafer (CtW) or chip-to-chip (CtC) processes in three-dimensional LSI integration. In this work we have optimized edge-trimming and back-grinding followed by chemical-mechanical polishing processes for WtW integration of 12-inch LSI wafer with thickness ≤ 50 μm. After optimization, we were able to achieve the total thickness variation (TTV) of less than 200 nm in the 50 μm-thick LSI wafers. Also, it was found that the smaller TTV value of temporarily bonded wafer before wafer thinning greatly helps to reduce the TTV in the back-ground and polished wafers. We successfully integrated 50 μm-thick 8- and 12-inch LSI wafers to their respective passive interposers using Cu-TSVs, and the electrical properties of TSVs were evaluated.

本文言語English
ホスト出版物のタイトル25th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ57-61
ページ数5
ISBN(印刷版)9781479939442
DOI
出版ステータスPublished - 2014
イベント25th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2014 - Saratoga Springs, NY, United States
継続期間: 2014 5 192014 5 21

出版物シリーズ

名前ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings
ISSN(印刷版)1078-8743

Other

Other25th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2014
国/地域United States
CitySaratoga Springs, NY
Period14/5/1914/5/21

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 工学(全般)
  • 産業および生産工学
  • 電子工学および電気工学

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