TY - JOUR
T1 - Wafer-scale fabrication of transistors using CVD-grown graphene and its application to inverter circuit
AU - Nakaharai, Shu
AU - Iijima, Tomohiko
AU - Ogawa, Shinichi
AU - Yagi, Katsunori
AU - Harada, Naoki
AU - Hayashi, Kenjiro
AU - Kondo, Daiyu
AU - Takahashi, Makoto
AU - Li, Songlin
AU - Tsukagoshi, Kazuhito
AU - Sato, Shintaro
AU - Yokoyama, Naoki
N1 - Publisher Copyright:
© 2015 The Japan Society of Applied Physics.
PY - 2015/4/1
Y1 - 2015/4/1
N2 - Graphene transistors were fabricated by a wafer-scale "top-down" process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.
AB - Graphene transistors were fabricated by a wafer-scale "top-down" process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.
UR - http://www.scopus.com/inward/record.url?scp=84926359864&partnerID=8YFLogxK
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U2 - 10.7567/JJAP.54.04DN06
DO - 10.7567/JJAP.54.04DN06
M3 - Article
AN - SCOPUS:84926359864
SN - 0021-4922
VL - 54
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
IS - 4
M1 - 04DN06
ER -