This paper presents a VLSI processor for reliable stereo matching to establish correspondence between images by selecting a desirable window size for sum of absolute differences (SAD) computation. In SAD computation, a degree of parallelism between pixels in a window changes depending on its window size, while a degree of parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is also proposed to achieve 100% utilization of processing elements. Not only 100% utilization but also a simple interconnection network between memory modules and processing elements makes the VLSI processor much superior to the pixel-parallel-architecture-based VLSI processors.
|出版ステータス||Published - 2004 9月 29|
|イベント||2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States|
継続期間: 2004 6月 17 → 2004 6月 19
|Other||2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI|
|Period||04/6/17 → 04/6/19|
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