VLSI-ORIENTED DIGITAL SIGNAL PROCESSOR BASED ON PULSE-TRAIN RESIDUE ARITHMETIC CIRCUIT WITH A MULTIPLIER.

Michitaka Kameyama, Oluwole Adegbenro, Tatsuo Higuchi

研究成果: Article査読

2 被引用数 (Scopus)

抄録

This paper proposes a new residue number multiplication scheme based on the cyclic type of relationship which exists between the entries in the residue number multiplication truth-table when the modulus is any prime number. Using the scheme, multiplication is direct without table consultation and an entire truth-table is realizable. The multiplier circuit is simple and compact and allows pipelined processing of data. The flexibility of the multiplier is exploited in the implementation of an RNS based high-order FIR digital filter by using a programmable low order section. The suitability of the modular digital processor for VLSI is also indicated.

本文言語English
ページ(範囲)14-21
ページ数8
ジャーナルTransactions of the Institute of Electronics and Communication Engineers of Japan. Section E
E68
1
出版ステータスPublished - 1985 1 1

ASJC Scopus subject areas

  • 工学(全般)

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