抄録
VLSI-oriented arithmetic circuits based on the signed-digital (SD) number system are proposed. A new bidirectional current-mode circuit in MOS technology is effectively used for SD number arithmetic operations. The circuit interconnections can be drastically reduced in spite of the redundant SD number representation. A VLSI-oriented, very fast SD multiplier is designed that is based on parallel binary-tree addition scheme. The multiply time of an SD array multiplier based on 2- mu m design rules is less than 30 ns.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings of The International Symposium on Multiple-Valued Logic |
| 出版社 | IEEE |
| ページ | 70-77 |
| ページ数 | 8 |
| ISBN（印刷版） | 0818606991 |
| 出版ステータス | Published - 1986 1月 1 |
ASJC Scopus subject areas
- 化学的な安全衛生
- ハードウェアとアーキテクチャ
- 安全性、リスク、信頼性、品質管理
- 論理