Unified scheduling of high performance parallel VLSI processors for robotics

Bumchul Kim, Michitaka Kameyama, Tatsuo Higuchi

研究成果: Article査読

1 被引用数 (Scopus)

抄録

The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraints conditions, the scheduling efficiently generates an optimal solution using a integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.

本文言語English
ページ(範囲)904-910
ページ数7
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E76-A
6
出版ステータスPublished - 1993 6 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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