In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.
|ジャーナル||Digest of Technical Papers - Symposium on VLSI Technology|
|出版ステータス||Published - 1994 12 1|
|イベント||Proceedings of the 1994 Symposium on VLSI Technology - Honolulu, HI, USA|
継続期間: 1994 6 7 → 1994 6 9
ASJC Scopus subject areas
- Electrical and Electronic Engineering