Ultrafast low-power operation of p+-n+ double-gate SOI MOSFETs

Tetsu Tanaka, Kunihiro Suzuki, Hiroshi Horie, Toshihiro Sugii

研究成果: Conference article査読

30 被引用数 (Scopus)


In this study, p+-n+ double-gate SOI MOSFET's have been fabricated using direct bonded SOI wafers just 40 nm thick. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. Obtained is an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V, for Lg = 0.19 μm. These are the fastest reported values for this gate length.

ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
出版ステータスPublished - 1994 12 1
イベントProceedings of the 1994 Symposium on VLSI Technology - Honolulu, HI, USA
継続期間: 1994 6 71994 6 9

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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