Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

Yukinori Morita, Koichi Fukuda, Yongxun Liu, Takahiro Mori, Wataru Mizubayashi, Shin Ichi O'Uchi, Hiroshi Fuketa, Shintaro Otsuka, Shinji Migita, Meishoku Masahara, Kazuhiko Endo, Hiroyuki Ota, Takashi Matsukawa

研究成果: Article査読

12 被引用数 (Scopus)

抄録

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

本文言語English
論文番号04CD19
ジャーナルJapanese journal of applied physics
56
4
DOI
出版ステータスPublished - 2017 4月

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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