Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

Yukinori Morita; Koichi Fukuda; Yongxun Liu; Takahiro Mori; Wataru Mizubayashi; Shin Ichi O'Uchi; Hiroshi Fuketa; Shintaro Otsuka; Shinji Migita; Meishoku Masahara; Kazuhiko Endo; Hiroyuki Ota; Takashi Matsukawa

doi:10.7567/JJAP.56.04CD19

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

Yukinori Morita, Koichi Fukuda, Yongxun Liu, Takahiro Mori, Wataru Mizubayashi, Shin Ichi O'Uchi, Hiroshi Fuketa, Shintaro Otsuka, Shinji Migita, Meishoku Masahara, Kazuhiko Endo, Hiroyuki Ota, Takashi Matsukawa

流体科学研究所・未到エネルギー研究センター

研究成果: Article › 査読

12 被引用数 (Scopus)

抄録

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

本文言語	English
論文番号	04CD19
ジャーナル	Japanese journal of applied physics
巻	56
号	4
DOI	https://doi.org/10.7567/JJAP.56.04CD19
出版ステータス	Published - 2017 4月

ASJC Scopus subject areas

工学（全般）
物理学および天文学（全般）

文献へのアクセス

10.7567/JJAP.56.04CD19

他のファイルとリンク

引用スタイル

Morita, Y., Fukuda, K., Liu, Y., Mori, T., Mizubayashi, W., O'Uchi, S. I., Fuketa, H., Otsuka, S., Migita, S., Masahara, M., Endo, K., Ota, H., & Matsukawa, T. (2017). Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application. Japanese journal of applied physics, 56(4), [04CD19]. https://doi.org/10.7567/JJAP.56.04CD19

@article{c6e5eb1e41bb4974bffaf397656d6dac,

title = "Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application",

abstract = "We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.",

author = "Yukinori Morita and Koichi Fukuda and Yongxun Liu and Takahiro Mori and Wataru Mizubayashi and O'Uchi, {Shin Ichi} and Hiroshi Fuketa and Shintaro Otsuka and Shinji Migita and Meishoku Masahara and Kazuhiko Endo and Hiroyuki Ota and Takashi Matsukawa",

note = "Publisher Copyright: {\textcopyright} 2017 The Japan Society of Applied Physics.",

year = "2017",

month = apr,

doi = "10.7567/JJAP.56.04CD19",

language = "English",

volume = "56",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

number = "4",

}

TY - JOUR

T1 - Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

AU - Morita, Yukinori

AU - Fukuda, Koichi

AU - Liu, Yongxun

AU - Mori, Takahiro

AU - Mizubayashi, Wataru

AU - O'Uchi, Shin Ichi

AU - Fuketa, Hiroshi

AU - Otsuka, Shintaro

AU - Migita, Shinji

AU - Masahara, Meishoku

AU - Endo, Kazuhiko

AU - Ota, Hiroyuki

AU - Matsukawa, Takashi

PY - 2017/4

Y1 - 2017/4

N2 - We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

AB - We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

UR - http://www.scopus.com/inward/record.url?scp=85017111162&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85017111162&partnerID=8YFLogxK

U2 - 10.7567/JJAP.56.04CD19

DO - 10.7567/JJAP.56.04CD19

M3 - Article

AN - SCOPUS:85017111162

VL - 56

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 4

M1 - 04CD19

ER -

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

抄録

ASJC Scopus subject areas

文献へのアクセス

他のファイルとリンク

フィンガープリント

引用スタイル