Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-To-Wafer Self-Assembly and Direct Bonding

T. Fukushima, H. Hashiguchi, H. Kino, T. Tanaka, M. Murugesan, J. Bea, H. Hashimoto, K. Lee, M. Koyanagi

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

Non-Transfer and transfer based 3D integration technologies are developed to achieve high-Throughput and high-precision multichip-To-wafer stacking. Both the stacking approaches employ KGD self-Assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-Treated plasma-TEOS SiO2 on their top surface are directly self-Assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-Assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.

本文言語English
ホスト出版物のタイトルProceedings - ECTC 2016
ホスト出版物のサブタイトル66th Electronic Components and Technology Conference
出版社Institute of Electrical and Electronics Engineers Inc.
ページ289-294
ページ数6
ISBN(電子版)9781509012039
DOI
出版ステータスPublished - 2016 8 16
イベント66th IEEE Electronic Components and Technology Conference, ECTC 2016 - Las Vegas, United States
継続期間: 2016 5 312016 6 3

出版物シリーズ

名前Proceedings - Electronic Components and Technology Conference
2016-August
ISSN(印刷版)0569-5503

Other

Other66th IEEE Electronic Components and Technology Conference, ECTC 2016
CountryUnited States
CityLas Vegas
Period16/5/3116/6/3

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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