TiN/W/La2O3/Si high-k gate stack for EOT below 0.5nm

P. Ahmet, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat, T. Kawanago, K. Kakushima, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai

研究成果: Conference contribution

抄録

Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved with a 3nm W inserted layer after annealed at 800°C in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates for realizing high-k gate stack with EOT of 0.5nm and beyond.

本文言語English
ホスト出版物のタイトルChina Semiconductor Technology International Conference 2011, CSTIC 2011
ページ99-102
ページ数4
1
DOI
出版ステータスPublished - 2011
外部発表はい
イベント10th China Semiconductor Technology International Conference 2011, CSTIC 2011 - Shanghai, China
継続期間: 2011 3 132011 3 14

出版物シリーズ

名前ECS Transactions
番号1
34
ISSN(印刷版)1938-5862
ISSN(電子版)1938-6737

Other

Other10th China Semiconductor Technology International Conference 2011, CSTIC 2011
国/地域China
CityShanghai
Period11/3/1311/3/14

ASJC Scopus subject areas

  • 工学(全般)

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