Timing optimization on mapped circuits

Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Sigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

Techniques for timing optimization of CMOS or BiCMOS gate array or standard cell circuits are presented. Based on previous works on critical path resynthesis, technology mapping algorithms using dynamic programming techniques, and fanout optimization algorithms, the following techniques were developed: a hierarchical data structure in which a circuit is partitioned into subcircuits, a weight function to gate subcircuits in terms of their potential for delay reduction, a critical path resynthesis technique preceded by noncritical path resynthesis, a mapping algorithm using tree covering techniques tightly coupled with a fanout optimization algorithm which can treat dual signals not only in sinks but also in sources, and a correction procedure for short paths. A program using these techniques achieves an average speedup of 37% with 27% increase in area on the DAC'86 benchmark set plus several additional circuits from actual designs.

本文言語English
ホスト出版物のタイトルProceedings - Design Automation Conference
出版社Publ by IEEE
ページ112-117
ページ数6
ISBN(印刷版)0818691492, 9780818691492
DOI
出版ステータスPublished - 1991
外部発表はい
イベントProceedings of the 28th ACM/IEEE Design Automation Conference - San Francisco, CA, USA
継続期間: 1991 6 171991 6 21

出版物シリーズ

名前Proceedings - Design Automation Conference
ISSN(印刷版)0146-7123

Conference

ConferenceProceedings of the 28th ACM/IEEE Design Automation Conference
CitySan Francisco, CA, USA
Period91/6/1791/6/21

ASJC Scopus subject areas

  • 工学(全般)

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