Three-dimensional shared memory fabricated using wafer stacking technology

K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, M. Koyanagi

研究成果: Conference article査読

107 被引用数 (Scopus)


We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 2000
イベント2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
継続期間: 2000 12 102000 12 13

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学
  • 材料化学


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