We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 2000|
|イベント||2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States|
継続期間: 2000 12 10 → 2000 12 13
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