Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

本文言語English
ホスト出版物のタイトルIEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOI
出版ステータスPublished - 2010 12 13
イベント32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
継続期間: 2010 9 192010 9 22

出版物シリーズ

名前Proceedings of the Custom Integrated Circuits Conference
ISSN(印刷版)0886-5930

Other

Other32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
CountryUnited States
CitySan Jose, CA
Period10/9/1910/9/22

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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