Three-dimensional integration technology using self-assembly technique and super-chip integration

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5μm. We have fabricated 3-D LSI test chips by a super-chip integration technology.

本文言語English
ホスト出版物のタイトル2008 IEEE International Interconnect Technology Conference, IITC
ページ10-12
ページ数3
DOI
出版ステータスPublished - 2008
イベント2008 IEEE International Interconnect Technology Conference, IITC - Burlingame, CA, United States
継続期間: 2008 6 12008 6 4

出版物シリーズ

名前2008 IEEE International Interconnect Technology Conference, IITC

Other

Other2008 IEEE International Interconnect Technology Conference, IITC
国/地域United States
CityBurlingame, CA
Period08/6/108/6/4

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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