抄録
A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings of the ASP-DAC 2009 |
| ホスト出版物のサブタイトル | Asia and South Pacific Design Automation Conference 2009 |
| ページ | 409-415 |
| ページ数 | 7 |
| DOI | |
| 出版ステータス | Published - 2009 4 20 |
| イベント | Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan 継続期間: 2009 1 19 → 2009 1 22 |
Other
| Other | Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 |
|---|---|
| Country | Japan |
| City | Yokohama |
| Period | 09/1/19 → 09/1/22 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications
- Computer Graphics and Computer-Aided Design