Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories

Chia Yin Liu, Yi Jung Chen, Masanori Hariyama

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Integrating Multi-Processor System-on-Chips (MPSoCs) and memories vertically by Through-Silicon Vias (TSVs) provides abundant memory bandwidth, but the increase of power density also makes the system frequently work under thermal emergent states. Although several thermal-aware TSV placement methods have been proposed to ease the thermal issue from the architectural design points of view, the overlooking of designing the type of stacked memories and memory interface in synergy may lead to thermal inefficient designs. The stacked memories may be SRAMs, DRAMs, or even NVMs, and they are divergent in power, performance, and thermal behavior, which in turn would greatly affect the memory interface design, i.e. TSV placements. In this paper, we propose the first thermal-aware memory system synthesis method for MPSoCs with 3D-stacked hybrid memories. The proposed method synergistically synthesizes the type of stacked memories and the memory interface aiming at optimizing performance while the thermal constraint is met. The results show that, among all the tested cases, the proposed method successfully keep peak temperature under 85°C with at most 29% of performance degradation.

本文言語English
ホスト出版物のタイトル35th Annual ACM Symposium on Applied Computing, SAC 2020
出版社Association for Computing Machinery
ページ546-553
ページ数8
ISBN(電子版)9781450368667
DOI
出版ステータスPublished - 2020 3月 30
イベント35th Annual ACM Symposium on Applied Computing, SAC 2020 - Brno, Czech Republic
継続期間: 2020 3月 302020 4月 3

出版物シリーズ

名前Proceedings of the ACM Symposium on Applied Computing

Conference

Conference35th Annual ACM Symposium on Applied Computing, SAC 2020
国/地域Czech Republic
CityBrno
Period20/3/3020/4/3

ASJC Scopus subject areas

  • ソフトウェア

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