@inproceedings{947e3b51821f48c3bcb8f1a4a20d415d,
title = "Theory of fermi level pinning of high-k dielectrics",
abstract = "Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high-work-function materials is governed by the O vacancy generation and subsequent formation of interface dipoles near gate electrodes due to the electron transfer. On the other hand, O interstitial formation plays a crucial role for Fermi-level pinning in low-work-function materials. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due the difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. The widening of this work-function pinning-free-region is the key issue for the fundamental relaxation of Fermi-level pinning in high-k gate dielectric.",
keywords = "Component, Fermi-level pinning, Flatband voltage shift, High-k dielectrics, Interface dipoles, Metal silicide gates, O interstitial, O vacancy, Poly-Si gates, Theory",
author = "Kenji Shiraishi and Yasushi Akasaka and Naoto Umezawa and Yasuo Nara and Keisaku Yamada and Hideki Takeuchi and Heiji Watanabe and Toyohiro Chikyow and Liu, {Tsu Jae King}",
year = "2006",
doi = "10.1109/SISPAD.2006.282897",
language = "English",
isbn = "1424404045",
series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "306--313",
booktitle = "2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06",
note = "2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06 ; Conference date: 06-09-2006 Through 08-09-2006",
}