Theory of fermi level pinning of high-k dielectrics

Kenji Shiraishi, Yasushi Akasaka, Naoto Umezawa, Yasuo Nara, Keisaku Yamada, Hideki Takeuchi, Heiji Watanabe, Toyohiro Chikyow, Tsu Jae King Liu

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high-work-function materials is governed by the O vacancy generation and subsequent formation of interface dipoles near gate electrodes due to the electron transfer. On the other hand, O interstitial formation plays a crucial role for Fermi-level pinning in low-work-function materials. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due the difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. The widening of this work-function pinning-free-region is the key issue for the fundamental relaxation of Fermi-level pinning in high-k gate dielectric.

本文言語English
ホスト出版物のタイトル2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06
出版社Institute of Electrical and Electronics Engineers Inc.
ページ306-313
ページ数8
ISBN(印刷版)1424404045, 9781424404049
DOI
出版ステータスPublished - 2006
外部発表はい
イベント2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06 - Monterey, CA, United States
継続期間: 2006 9月 62006 9月 8

出版物シリーズ

名前International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06
国/地域United States
CityMonterey, CA
Period06/9/606/9/8

ASJC Scopus subject areas

  • 工学(全般)

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