The performance of magnetic tunnel junction integrated on the back-end metal line of complimentary metal-oxide-semiconductor circuits

Tetsuo Endoh, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Masashi Kamiyanagi, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno

研究成果: Article査読

抄録

In this paper, we have described the complementary metal-oxide- semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3nm with 0.14 μ CMOS process and 60 × 180nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kω (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.

本文言語English
論文番号04DM06
ジャーナルJapanese journal of applied physics
49
4 PART 2
DOI
出版ステータスPublished - 2010 4月 1

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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