We have proposed a wafer stacking technology to integrate various kinds of devices into three-dimensional (3D) SoC[1-6]. In 3D SoC, each circuit layer is stacked and electrically connected vertically using a huge number of vertical interconnection. Hence, we can dramatically increase the wiring connectivity, reduce the number of long wiring and integrate various kinds of devices with different fabrication process sequences into one chip. In this paper, we describe a 3D microprocessor test chip consisting of three circuit layers and demonstrate the basic operation of the 3D microprocessor.
|出版ステータス||Published - 2004 12 1|
|イベント||2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China|
継続期間: 2004 10 18 → 2004 10 21
|Other||2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004|
|Period||04/10/18 → 04/10/21|
ASJC Scopus subject areas