Technology for three dimensional integrated system-on-a-chip

Hiroyuki Kurino, Mitsumasa Koyanagi

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

We have proposed a wafer stacking technology to integrate various kinds of devices into three-dimensional (3D) SoC[1-6]. In 3D SoC, each circuit layer is stacked and electrically connected vertically using a huge number of vertical interconnection. Hence, we can dramatically increase the wiring connectivity, reduce the number of long wiring and integrate various kinds of devices with different fabrication process sequences into one chip. In this paper, we describe a 3D microprocessor test chip consisting of three circuit layers and demonstrate the basic operation of the 3D microprocessor.

本文言語English
ページ599-602
ページ数4
出版ステータスPublished - 2004 12 1
イベント2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China
継続期間: 2004 10 182004 10 21

Other

Other2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
国/地域China
CityBeijing
Period04/10/1804/10/21

ASJC Scopus subject areas

  • 工学(全般)

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