Systolic computational-memory architecture for an FPGA-based flow solver

Kentaro Sano, Takanori Iizuka, Satoru Yamamoto

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

This paper presents an FPGA-based flow solver based on the systolic computational-memory architecture. We show that the flow solver based on the fractional-step method with difference schemes can be expressed as a systolic algorithm, and the systolic computationalmemory architecture is suitable to design the special-purpose processor for the flow solver. Based on this architecture, we propose a specialpurpose processor comprised of a 2D array of cells connected by a 2D mesh network. Each cell has a computational data-path and a local memory, While the whole array stores data as a memory, it also performs highly parallel and scalable floating-point computations with the sufficient memory bandwidth. We report the initial design of the processor for two ALTERA Stratix II FPGAs, and discuss its estimated peak performance that could reach 30 GFLOPS at only 60MHz.

本文言語English
ホスト出版物のタイトルProceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
ページ423-427
ページ数5
DOI
出版ステータスPublished - 2006
イベント2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06 - San Juan, Puerto Rico
継続期間: 2006 8月 62007 8月 9

出版物シリーズ

名前Midwest Symposium on Circuits and Systems
1
ISSN(印刷版)1548-3746

Other

Other2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06
国/地域Puerto Rico
CitySan Juan
Period06/8/607/8/9

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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