Systolic architecture for computational fluid dynamics on FPGAs

Kentaro Sano, Takanori Iizuka, Satoru Yamamoto

研究成果: Conference contribution

41 被引用数 (Scopus)

抄録

This paper presents an FPGA-based flow solver based on the systolic architecture. We show that the fractionalstep method employing central difference schemes can be expressed as a systolic algorithm, and therefore the systolic architecture is suitable for a dedicated processor to the flow solver. We have designed a 2D systolic array of cells, each of which has a micro-programmable data-path containing a MAC (multiplication and accumulation) unit and a local memory to store necessary data for computational fluid dynamics. With ALTERA Stratix II FPGA, we implemented 96(= 12 x 8) cells running at 60MHz. Since the MAC unit has both an adder and a multiplier for single-precision floating-point numbers, the total peak performance is 11.5(= 96 x 6MHz x 2) GFlops. We made a choice of 2D square driven cavity flow as a benchmark computation based on the fractional-step method. For this computation, the FPGA-based processor running only at 60MHz achieved 7.14 and 6.41 times faster computations than Pentium4 processor at 3.2 GHz and Itanium2 at 1.4 GHz, respectively.

本文言語English
ホスト出版物のタイトルProceedings 2007 IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2018
出版社IEEE Computer Society
ページ107-116
ページ数10
ISBN(印刷版)0769529402, 9780769529400
DOI
出版ステータスPublished - 2007 1月 1
イベント15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007 - Napa, CA, United States
継続期間: 2007 4月 232007 4月 25

出版物シリーズ

名前Proceedings 2007 IEEE Symposium on Field-Programme Custom Computing Machines, FCCM 2007

Other

Other15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007
国/地域United States
CityNapa, CA
Period07/4/2307/4/25

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • ソフトウェア
  • 電子工学および電気工学

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