Systematic design of RSA processors based on high-radix montgomery multipliers

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

研究成果: Article査読

65 被引用数 (Scopus)

抄録

This paper presents a systematic design approach to provide the optimized RivestShamirAdleman (RSA) processors based on high-radix Montgomery multipliers satisfying various user requirements, such as circuit area, operating time, and resistance against side-channel attacks. In order to involve the tradeoff between the performance and the resistance, we apply four types of exponentiation algorithms: two variants of the binary method with/without Chinese Remainder Theorem (CRT). We also introduces three multiplier-based datapath-architectures using different intermediate data forms: 1) single form, 2) semi carry-save form, and 3) carry-save form, and combined them with a wide variety of arithmetic components. Their radices are parameterized from 2 8 to 2128. A total of 242 datapaths for 1024-bit RSA processors were obtained for each radix. The potential of the proposed approach is demonstrated through an experimental synthesis of all possible processors with a 90-nm CMOS standard cell library. As a result, the smallest design of 861 gates with 118.47 ms/RSA to the fastest design of 0.67 ms/RSA at 153 862 gates were obtained. In addition, the use of the CRT technique reduced the RSA operation time of the fastest design to 0.24 ms. Even if we employed the exponentiation algorithm resistant to typical side-channel attacks, the fastest design can perform the RSA operation in less than 1.0 ms.

本文言語English
論文番号5497217
ページ(範囲)1136-1146
ページ数11
ジャーナルIEEE Transactions on Very Large Scale Integration (VLSI) Systems
19
7
DOI
出版ステータスPublished - 2011 7月

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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