Systematic approach to designing multiple-valued arithmetic circuits based on arithmetic description language

Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

研究成果: Article査読

抄録

This paper proposes a high-level design method of multiple-valued arithmetic circuits. The proposed method uses a cell-based approach with a dedicated hardware description language called ARITH. By using ARITH, we can describe and verify any binary/multiple-valued arithmetic circuits in a formal manner. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelfplace-and-route tool. In this paper, we present a specific cell library containing a multiple-valued signed-digit adder and its related circuits with a 0.35 μm CMOS technology, and demonstrate that the proposed method can synthesize a 32 × 32-bit parallel multiplier in multiple-valued current-mode logic from an ARITH description.

本文言語English
ページ(範囲)329-340
ページ数12
ジャーナルJournal of Multiple-Valued Logic and Soft Computing
15
4
出版ステータスPublished - 2009 11 18

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic

フィンガープリント 「Systematic approach to designing multiple-valued arithmetic circuits based on arithmetic description language」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル