Suppression of anomalous threshold voltage increase with area scaling for Mg- or La-incorporated high-k/metal gate nMISFETs in deeply scaled region

T. Morooka, M. Sato, T. Matsuki, T. Suzuki, K. Shiraishi, A. Uedono, S. Miyazaki, K. Ohmori, K. Yamada, T. Nabatame, T. Chikyow, J. Yugami, K. Ikeda, Y. Ohji

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for Vt reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The key to suppress the area scaling dependence is pilling Mg or La atoms up near high-k/IFL interface which enable us increase of stable capping effect. Combination of processing for high-k gate dielectrics and device structure with the high-k dielectrics under offset spacers was found to effectively suppress the Vt increase at the 100 nm channel width. As a conclusion, the large capping effect for Vt reduction over 400 mV is achieved in scaled devices using this technique.

本文言語English
ホスト出版物のタイトル2010 Symposium on VLSI Technology, VLSIT 2010
ページ33-34
ページ数2
DOI
出版ステータスPublished - 2010
外部発表はい
イベント2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
継続期間: 2010 6月 152010 6月 17

出版物シリーズ

名前Digest of Technical Papers - Symposium on VLSI Technology
ISSN(印刷版)0743-1562

Other

Other2010 Symposium on VLSI Technology, VLSIT 2010
国/地域United States
CityHonolulu, HI
Period10/6/1510/6/17

ASJC Scopus subject areas

  • 電子工学および電気工学

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