Super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-μm GaAs MESFETs

Taiichi Otsuji, Mikio Yoneyama, Koichi Murata, Eiichi Sano

研究成果: Paper査読

19 被引用数 (Scopus)

抄録

This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-μm GaAs MESFET technology.

本文言語English
ページ145-148
ページ数4
出版ステータスPublished - 1996 12 1
外部発表はい
イベントProceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Orlando, FL, USA
継続期間: 1996 11 31996 11 6

Other

OtherProceedings of the 1996 18th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
CityOrlando, FL, USA
Period96/11/396/11/6

ASJC Scopus subject areas

  • 電子工学および電気工学

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