Sub-1-V-60nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

Ryosuke Ogasawara, Tetsuo Endoh

研究成果: Article査読

抄録

In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90nm planar MOSFET whose gate length and channel width are the same as those of the 60nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

本文言語English
論文番号04FE12
ジャーナルJapanese journal of applied physics
57
4
DOI
出版ステータスPublished - 2018 4

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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