Study of Stochastic Invertible Multiplier Designs

Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Invertible logic is a method of reversible computing that can propagate a circuit signal backward from outputs. For example, not only multiplication (forward operation) but also division and factorization (backward operation) can be performed by this circuit style of a single multiplier. Currently, invertible logic has been able to realize only small-scale circuits. In this paper, we design larger-scale circuits than that reported conventionally, using stochastic computing. Furthermore, we also verify the performance of invertible logic using three different multipliers.

本文言語English
ホスト出版物のタイトル2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ページ649-650
ページ数2
ISBN(電子版)9781538695623
DOI
出版ステータスPublished - 2019 1 17
イベント25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 - Bordeaux, France
継続期間: 2018 12 92018 12 12

出版物シリーズ

名前2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

Conference

Conference25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
国/地域France
CityBordeaux
Period18/12/918/12/12

ASJC Scopus subject areas

  • 電子工学および電気工学
  • 器械工学

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