TY - JOUR
T1 - Structural dependence on device characteristics for sidewall base contact structure transistor
AU - Washio, Katsuyoshi
AU - Nakazato, Kazuo
AU - Nakamura, Tohru
PY - 1990
Y1 - 1990
N2 - Although silicon bipolar transistors have realized high‐speed characteristics by the development of self‐aligned techniques, the miniaturization of each part of the device structure is important to realize further improvement in operation speed. This paper considers the width of the sidewall contact between a base polysilicon and single crystal silicon, which is a characteristic structural parameter for sidewall base contact structure (SICOS). Also, its effect on the transistor characteristics and ECL circuit characteristics is examined. As a result, it has been shown that the sidewall contact width determines the lateral diffusion length of the external base and affects the transistor characteristics concerning emitter‐base junction and external base‐intrinsic base link‐up. The transistor characteristics dependent on the separation between the external base and n+ buried layer is also clarified. As for the ECL circuit performance, the effect of structural parameters has been examined from the relation between its delay components and transistor characteristics, and the method for design optimization is shown.
AB - Although silicon bipolar transistors have realized high‐speed characteristics by the development of self‐aligned techniques, the miniaturization of each part of the device structure is important to realize further improvement in operation speed. This paper considers the width of the sidewall contact between a base polysilicon and single crystal silicon, which is a characteristic structural parameter for sidewall base contact structure (SICOS). Also, its effect on the transistor characteristics and ECL circuit characteristics is examined. As a result, it has been shown that the sidewall contact width determines the lateral diffusion length of the external base and affects the transistor characteristics concerning emitter‐base junction and external base‐intrinsic base link‐up. The transistor characteristics dependent on the separation between the external base and n+ buried layer is also clarified. As for the ECL circuit performance, the effect of structural parameters has been examined from the relation between its delay components and transistor characteristics, and the method for design optimization is shown.
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U2 - 10.1002/ecjb.4420730510
DO - 10.1002/ecjb.4420730510
M3 - Article
AN - SCOPUS:0025433554
VL - 73
SP - 81
EP - 90
JO - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
JF - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
SN - 8756-663X
IS - 5
ER -