Strain enhanced FUSI/HfSiON technology with optimized CMOS process window

A. Veloso, P. Verheyen, R. Vos, S. Brus, S. Ito, R. Mitsuhashi, V. Paraschiv, X. Shi, B. Onsia, S. Arnauts, R. Loo, A. Lauwers, T. Conard, J. F. De Marneffe, D. Goossens, D. Baute, S. Locorotondo, T. Chiarella, C. Kerner, C. VranckenS. Mertens, B. J. O'Sullivan, H. Y. Yu, S. Z. Chang, Masaaki Niwa, J. A. Kittl, P. P. Absil, M. Jurczak, T. Hoffmann, S. Biesemans

研究成果: Conference article

2 引用 (Scopus)

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We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V T NMOS and PMOS devices with 725/370 μA/μm (at V DD =1.1V, Ioff=20pA/μm and Jg=100/1 mA/cm 2 ). We demonstrate that adding embedded Si 0.75 Ge 0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni 31 Si 12 or Ni 2 Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shining up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSI; - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.

元の言語English
記事番号4339692
ページ(範囲)200-201
ページ数2
ジャーナルDigest of Technical Papers - Symposium on VLSI Technology
DOI
出版物ステータスPublished - 2007 12 1
外部発表Yes
イベント2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
継続期間: 2007 6 122007 6 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Veloso, A., Verheyen, P., Vos, R., Brus, S., Ito, S., Mitsuhashi, R., Paraschiv, V., Shi, X., Onsia, B., Arnauts, S., Loo, R., Lauwers, A., Conard, T., De Marneffe, J. F., Goossens, D., Baute, D., Locorotondo, S., Chiarella, T., Kerner, C., ... Biesemans, S. (2007). Strain enhanced FUSI/HfSiON technology with optimized CMOS process window. Digest of Technical Papers - Symposium on VLSI Technology, 200-201. [4339692]. https://doi.org/10.1109/VLSIT.2007.4339692