STEPPED ELECTRODE TRANSISTOR: SET.

Tetsushi Sakai, Yoshio Sunohara, Yutaka Sakakibara, Junichi Murota

研究成果: Paper査読

4 被引用数 (Scopus)

抄録

SET can achieve high performance without precise photolithography and metallization techniques. An arsenic doped polycrystalline silicon is used as a part of the emitter electrode in the SET structure. It is processed to have an inverse trapezoid shape. Procedure to make the inverse trapezoid shape uses a difference of etching rates between double layers of polycrystalline silicon. Base contact windows are opened through the ion-implantation process followed by chemical etching. The cut off frequency is about 8. 4 GHz. This frequency is higher than that of the conventional planar transistors with equal size emitter by 2 GHz.

本文言語English
ページ43-46
ページ数4
出版ステータスPublished - 1977 1 1
イベントProc Conf Solid State Devices 8th - Tokyo, Jpn
継続期間: 1976 9 11976 9 3

Other

OtherProc Conf Solid State Devices 8th
CityTokyo, Jpn
Period76/9/176/9/3

ASJC Scopus subject areas

  • 工学(全般)

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