Spintronics primitive gate with high error correction efficiency 6(P error) 2 for logic-in memory architecture

Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

A spintronics primitive gate with redundancy was designed using domain wall motion (DWM) cells, and the data-missing rate was drastically improved to ∼ 6 (P error) 2 when the error rate per DWM cell was P error. All the DWM cells aligned in series were written simultaneously, which suppressed the increase in power consumption when writing. Application of 4-terminal DWM cells with physically separated current paths for writing and reading saved extra path transistors for redundancy and there were no area overheads.

本文言語English
ホスト出版物のタイトル2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
ページ63-64
ページ数2
DOI
出版ステータスPublished - 2012 9 27
イベント2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
継続期間: 2012 6 122012 6 14

出版物シリーズ

名前Digest of Technical Papers - Symposium on VLSI Technology
ISSN(印刷版)0743-1562

Other

Other2012 Symposium on VLSI Technology, VLSIT 2012
国/地域United States
CityHonolulu, HI
Period12/6/1212/6/14

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「Spintronics primitive gate with high error correction efficiency 6(P <sub>error</sub>) <sup>2</sup> for logic-in memory architecture」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル