SiGe-HBT-based 54-Gb/s 4:1 Multiplexer IC with full-rate clock for serial communication systems

Toru Masuda, Kenichi Ohhata, Nobuhiro Shiramizu, Eiji Ohue, Katsuya Oda, Reiko Hayami, Hiromi Shimamoto, Masao Kondo, Takashi Harada, Katsuyoshi Washio

研究成果: Article査読

7 被引用数 (Scopus)

抄録

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f T 0.2-μm self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10-12) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.

本文言語English
ページ(範囲)791-795
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
40
3
DOI
出版ステータスPublished - 2005 3
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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