Si substrate resistivity design for on-chip matching circuit based on electro-magnetic simulation

Masayoshi Ono, Noriharu Suematsu, Shunji Kubo, Kensuke Nakajima, Yoshitada Iyama, Tadashi Takagi, Osami Ishida

研究成果: Article査読

10 被引用数 (Scopus)

抄録

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electromagnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.

本文言語English
ページ(範囲)923-930
ページ数8
ジャーナルIEICE Transactions on Electronics
E84-C
7
出版ステータスPublished - 2001 7
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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