Self-assembly technology for reconfigured wafer-to-wafer 3D integration

T. Fukushima, E. Iwata, K. W. Lee, T. Tanaka, M. Koyanagi

研究成果: Conference contribution

23 被引用数 (Scopus)

抄録

We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously selfassembled to a carrier wafer named "reconfigured wafer". High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions. In addition, we developed a new self-assembled multichip bonder to three-dimensionally stack many known good dies (KDGs) on 8-inch wafers at the wafer level. By using the equipment, the many self-assembled Si chips were transferred to another target wafer in batch.

本文言語English
ホスト出版物のタイトル2010 Proceedings 60th Electronic Components and Technology Conference, ECTC 2010
ページ1050-1055
ページ数6
DOI
出版ステータスPublished - 2010 8月 9
イベント60th Electronic Components and Technology Conference, ECTC 2010 - Las Vegas, NV, United States
継続期間: 2010 6月 12010 6月 4

出版物シリーズ

名前Proceedings - Electronic Components and Technology Conference
ISSN(印刷版)0569-5503

Other

Other60th Electronic Components and Technology Conference, ECTC 2010
国/地域United States
CityLas Vegas, NV
Period10/6/110/6/4

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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