Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm

K. Kakushima, K. Okamoto, T. Koyanagi, K. Tachi, M. Kouda, T. Kawanago, J. Song, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Lwai

    研究成果: Conference contribution

    1 引用 (Scopus)

    抜粋

    An aggressive EOT scaling with high-k gate dielectrics has been presented by selection of a rare earth silicate (La, Ce and Pr) as an interfacial layer with La2O3 stacking. Among silicates, La2O 3/Ce-silicate nFET has performed a small EOT of 0.51 nm with a reduced gate leakage current of 102 A/cm2. SrO capping further reduces the gate leakage current also with a smaller EOT with improved subthreshold slope. A guideline for EOT scaling using RE-silicate in combination with SrO capping is proposed.

    元の言語English
    ホスト出版物のタイトルESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
    ページ403-406
    ページ数4
    DOI
    出版物ステータスPublished - 2009 12 1
    イベント39th European Solid-State Device Research Conference, ESSDERC 2009 - Athens, Greece
    継続期間: 2009 9 142009 9 18

    出版物シリーズ

    名前ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

    Other

    Other39th European Solid-State Device Research Conference, ESSDERC 2009
    Greece
    Athens
    期間09/9/1409/9/18

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Safety Research

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  • これを引用

    Kakushima, K., Okamoto, K., Koyanagi, T., Tachi, K., Kouda, M., Kawanago, T., Song, J., Ahmet, P., Tsutsui, K., Sugii, N., Hattori, T., & Lwai, H. (2009). Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm. : ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference (pp. 403-406). [5331331] (ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference). https://doi.org/10.1109/ESSDERC.2009.5331331