Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM with 10 ns Low Power Write Operation, 10 years Retention and Endurance 10-11

S. Miura, K. Nishioka, H. Naganuma, T. V.A. Nguyen, H. Honjo, S. Ikeda, T. Watanabe, H. Inoue, M. Niwa, T. Tanigawa, Y. Noguchi, T. Yoshiduka, M. Yasuhira, T. Endoh

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

We have firstly fabricated quad-interface perpendicular MTJ (Quad-MTJ) down to 33 nm with our developed PVD, RIE and damage control integration process technologies under 300 mm process. Secondly, we demonstrated scalability merit as well as high speed writing of Quad-MTJ compared with double-interface p-MTJ (Double-MTJ) as follows; (a) two times larger thermal stability factor δ(1X nm Quad- MTJ is extrapolated to achieve 10 years retention.), (b) lower write voltage at short write pulse regions at less than 30 ns, (c) in scaled MTJ, effective suppression of write current increase for higher write speed, (d) more than 2 times higher write efficiency at 10ns write operation down to 33 nm MTJ. Finally, we revealed that our developed 33 nm Quad-MTJ achieve excellent endurance of more 1011 thanks to higher write efficiency and low damage integration process technology. These results show that the Quad-MTJ technology is one of promising way for low power, high speed and enough reliable STT -MRAM with excellent scalability down to 1X nm node.

本文言語English
ホスト出版物のタイトル2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728164601
DOI
出版ステータスPublished - 2020 6
イベント2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 - Honolulu, United States
継続期間: 2020 6 162020 6 19

出版物シリーズ

名前Digest of Technical Papers - Symposium on VLSI Technology
2020-June
ISSN(印刷版)0743-1562

Conference

Conference2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
国/地域United States
CityHonolulu
Period20/6/1620/6/19

ASJC Scopus subject areas

  • 電子工学および電気工学

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