Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM with 10-ns Low Power Write Operation, 10 Years Retention and Endurance > 10¹¹

Sadahiko Miura, Koichi Nishioka, Hiroshi Naganuma, T. V.A. Nguyen, Hiroaki Honjo, Shoji Ikeda, Toshinari Watanabe, Hirofumi Inoue, Masaaki Niwa, Takaho Tanigawa, Yasuo Noguchi, Toru Yoshizuka, Mitsuo Yasuhira, Tetsuo Endoh

研究成果: Article査読

6 被引用数 (Scopus)

抄録

We fabricated a quadruple-interface perpendicular magnetic tunnel junction (MTJ) (Quad-MTJ) down to 33 nm using physical vapor-deposition, reactive ion etching, and damage-control integration process technologies that we developed under a 300-mm process. We demonstrated the greater scalability and higher writing speed of Quad-MTJ compared with double-interface perpendicular MTJ: 1) it has twice the thermal stability factor - 1X nm Quad-MTJ can achieve 10 years retention - while maintaining a low resistance-area product and high tunnel magnetoresistance ratio; 2) smaller overdrive ratio of write voltage to obtain a sufficiently low write-error rate; 2) smaller pulsewidth dependence of the switching current; and 4) more than double the write efficiency at 10-ns write operation down to 33-nm MTJ. The effective suppression of the switching current increase for higher write speeds was explained by the spin-transfer-torque model using the Fokker-Planck equation. Our 33-nm Quad-MTJ also achieved excellent endurance (at least 1011) owing to its higher write efficiency and low-damage integration-process technology. It is thus a promising method for low power, high speed, and reliable STT-MRAM with excellent scalability down to the 1X nm node.

本文言語English
論文番号9212560
ページ(範囲)5368-5373
ページ数6
ジャーナルIEEE Transactions on Electron Devices
67
12
DOI
出版ステータスPublished - 2020 12

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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