Review of STT-MRAM circuit design strategies, and a 40-nm 1T-1MTJ 128Mb STT-MRAM design practice

Hiroki Koike, Takaho Tanigawa, Toshinari Watanabe, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Toru Yoshiduka, Yitao Ma, Hiroaki Honjo, Koichi Nishioka, Sadahiko Miura, Hirofumi Inoue, Shoji Ikeda, Tetsuo Endoh

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

STT-MRAM is now an essential component for future low power consumption electronics. Recently, a number of STT-MRAM developments have been successively disclosed by major LSI vendors [1] -[9], and some of them announced that risk mass-production of STT-MRAM had started. This invited paper reviews, in this opportunity, STT-MRAM circuit design strategies, which cover memory cell design, sense amplifier (S/A) and reference generator (Refgen), and array architecture. Furthermore, as one example of STT-MRAM design, a 128Mb STT-MRAM chip using 40-nm standard CMOS and 3X-nm MTJ technology will be presented [10].

本文言語English
ホスト出版物のタイトル2020 IEEE 31st Magnetic Recording Conference, TMRC 2020
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728161778
DOI
出版ステータスPublished - 2020 8 17
イベント31st IEEE Magnetic Recording Conference, TMRC 2020 - Berkeley, United States
継続期間: 2020 8 172020 8 20

出版物シリーズ

名前2020 IEEE 31st Magnetic Recording Conference, TMRC 2020

Conference

Conference31st IEEE Magnetic Recording Conference, TMRC 2020
国/地域United States
CityBerkeley
Period20/8/1720/8/20

ASJC Scopus subject areas

  • メディア記述

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