Reduced-complexity binary-weight-coded associative memories

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross

研究成果: Conference contribution

16 被引用数 (Scopus)

抄録

Associative memories retrieve stored information given partial or erroneous input patterns. Recently, a new family of associative memories based on Clustered-Neural-Networks (CNNs) was introduced that can store many more messages than classical Hopfield-Neural Networks (HNNs). In this paper, we propose hardware architectures of such memories for partial or erroneous inputs. The proposed architectures eliminate winner-take-all modules and thus reduce the hardware complexity by consuming 65% fewer FPGA lookup tables and increase the operating frequency by approximately 1.9 times compared to that of previous work.

本文言語English
ホスト出版物のタイトル2013 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013 - Proceedings
ページ2523-2527
ページ数5
DOI
出版ステータスPublished - 2013 10 18
外部発表はい
イベント2013 38th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013 - Vancouver, BC, Canada
継続期間: 2013 5 262013 5 31

出版物シリーズ

名前ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ISSN(印刷版)1520-6149

Other

Other2013 38th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013
国/地域Canada
CityVancouver, BC
Period13/5/2613/5/31

ASJC Scopus subject areas

  • ソフトウェア
  • 信号処理
  • 電子工学および電気工学

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