In the recent sub-90nm VLSI generation, a fluctuation exists in a supply voltage due to IR-drop and inductance effects. A supply voltage fluctuation in VLSI chips causes large variations in the logic delay time and power consumption. However, in conventional low-power VLSI architecture such as variable threshold voltage CMOS (VTCMOS), the threshold voltage of a transistor is fixed in advance at the system design level. As a result,.VTCMOS can't compensate a supply voltage fluctuation. By employing an adaptive threshold voltage control (ATVC), minimization of power consumption under a time constraint is achieved even in the presence of a supply voltage fluctuation. Optimal granularity is discussed to minimize the total power consumption.