Ray tracing hardware system using plane-sphere intersections

Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Kenichi Suzuki, Tadao Nakamura, Nobuyuki Ohba

研究成果: Conference contribution

抄録

Ray tracing is a global illumination based rendering method widely used in computer graphics. Although it generates photo-realistic images, it requires a large number of computations. In ray tracing, the ray-object intersection test is one of the dominant factors for the processing speed. To accelerate the intersection test, we propose a new method based on a plane-sphere intersection algorithm, and show a hardware system using an FPGA. The computations used in the method are highly pipelined and parallelized by optimizing the balance between the computation speed and the memory data bandwidth. As a result, the prototype makes full use of 512 DSP cores built in Xilinx Vertex-4 SX FPGA, and the average utilization of the DSP cores is close to 90%. The simulation results show that the proposed system running at 160MHz performs the intersection test a few hundred times faster than a commodity PC with a 3.4GHz Pentium 4.

本文言語English
ホスト出版物のタイトルProceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
ページ315-320
ページ数6
DOI
出版ステータスPublished - 2006 12 1
イベント2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, Spain
継続期間: 2006 8 282006 8 30

出版物シリーズ

名前Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Other

Other2006 International Conference on Field Programmable Logic and Applications, FPL
国/地域Spain
CityMadrid
Period06/8/2806/8/30

ASJC Scopus subject areas

  • 計算理論と計算数学
  • 電子工学および電気工学

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