Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors

Rihito Kuroda, Akinobu Teramoto, Shigetoshi Sugawa

研究成果: Conference contribution

10 引用 (Scopus)

抜粋

Using the developed array test circuit, both static and temporal electrical characteristics of over million transistors/shot were measured with the accuracy of 60 μVrms to analyze and reduce random telegraph noise (RTN) toward high S/N CMOS image sensors. Statistical evaluation results of RTN parameters such as time constants and amplitude and their behaviors toward transistor device structures and operation conditions are summarized. Application to high S/N CMOS image sensor is also described.

元の言語English
ホスト出版物のタイトル2016 29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Conference Proceedings
出版者Institute of Electrical and Electronics Engineers Inc.
ページ46-51
ページ数6
ISBN(電子版)9781467387934
DOI
出版物ステータスPublished - 2016 5 20
イベント29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Yokohama, Japan
継続期間: 2016 3 282016 3 31

出版物シリーズ

名前IEEE International Conference on Microelectronic Test Structures
2016-May

Other

Other29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016
Japan
Yokohama
期間16/3/2816/3/31

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Kuroda, R., Teramoto, A., & Sugawa, S. (2016). Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors. : 2016 29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Conference Proceedings (pp. 46-51). [7476172] (IEEE International Conference on Microelectronic Test Structures; 巻数 2016-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICMTS.2016.7476172