A quaternary gate array for high-speed pattern matching, based on totally parallel structure, is presented. This gate array can be used in real-time applications when the rules are fixed. The chip can be implemented by a standard NMOS process with multiple ion implants. The rules can be programmed by setting the threshold of the transistor to one of the four states. It is demonstrated that the chip area for pattern matching can be reduced by 30% compared with the corresponding binary gate array.
|ホスト出版物のタイトル||Proceedings of The International Symposium on Multiple-Valued Logic|
|出版ステータス||Published - 1987 1 1|
|名前||Proceedings of The International Symposium on Multiple-Valued Logic|
ASJC Scopus subject areas
- Computer Science(all)