QUATERNARY GATE ARRAY FOR PATTERN MATCHING AND ITS APPLICATION TO KNOWLEDGE INFORMATION PROCESSING SYSTEM.

Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

A quaternary gate array for high-speed pattern matching, based on totally parallel structure, is presented. This gate array can be used in real-time applications when the rules are fixed. The chip can be implemented by a standard NMOS process with multiple ion implants. The rules can be programmed by setting the threshold of the transistor to one of the four states. It is demonstrated that the chip area for pattern matching can be reduced by 30% compared with the corresponding binary gate array.

本文言語English
ホスト出版物のタイトルProceedings of The International Symposium on Multiple-Valued Logic
出版社IEEE
ページ181-187
ページ数7
ISBN(印刷版)0818607750
出版ステータスPublished - 1987 1 1

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
ISSN(印刷版)0195-623X

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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