Pr3Si6N11/Si3N4 stacked high-k gate dielectrics with high quality ultrathin Si3N 4 interfacial layers

Tadahiro Ohmi, Hidetoshi Wakamatsu, Akinobu Teramoto

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

In Order to utilize the entire capability of the silicon crystal, we must fabricate LSI on any crystal orientation silicon surface using three dimensional structure MOS transistors, i.e., very high integrity gate insulator films must be formed on any crystal orientation silicon surface with the same formation speed, i.e., the radical oxidation (SiO2) and the radical nitridation (Si3N4) at low temperatures. Accumulation mode balanced CMOS fabricated on (551) surface silicon SOI substrate has been theoretically confirmed to exhibit super high speed performance over 100 GHz clock rate at 45 nm technology node where the gate insulator film to silicon interface is atomically flat and the series resistance of the source and the drain electrode is decreased by a factor of two orders of magnitude by introducing very low contact resistance new suicide materials to n+ region (ErSi 2) and p+ region (Pr2Si), respectively.

本文言語English
ホスト出版物のタイトルSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications
出版社Electrochemical Society Inc.
ページ275-284
ページ数10
2
ISBN(電子版)9781607682134
ISBN(印刷版)9781566778633
DOI
出版ステータスPublished - 2011

出版物シリーズ

名前ECS Transactions
番号2
35
ISSN(印刷版)1938-5862
ISSN(電子版)1938-6737

ASJC Scopus subject areas

  • 工学(全般)

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