Performance evaluation of a multivalued rsa encryption vlsi

Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi, Members

研究成果: Article査読

1 被引用数 (Scopus)

抄録

This paper discusses performance evaluation of a multiple‐valued RSA encryption VLSI based on radix‐4 signed‐digit (SD) number arithmetic that is very useful for long word length arithmetic. In the arithmetic unit of the encryption VLSI, a signed‐digit adder (SD adder) is used, which is constructed with bidirectional current‐mode circuits. Also, the input/output interface circuit of the radix‐4 adder is considered for construction of a high‐speed SD full adder. A layout of the encryption VLSI including this multiple‐valued SD full adder is designed by the 2‐m̈m CMOS rule and the chip size is 9.1 7.4 mm2 for 512‐bit word length encryption. By performance evaluation with extracting SPICE parameters from the layout, an encryption rate of 85 bit/s can be obtained which is a factor of eight times faster than that of the corresponding binary one.

本文言語English
ページ(範囲)12-21
ページ数10
ジャーナルSystems and Computers in Japan
22
7
DOI
出版ステータスPublished - 1991 1 1

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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