Perceptron-based Cache Bypassing for Way-Adaptable Caches

Masayuki Sato, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi

研究成果: Conference contribution

抄録

A way-adaptable cache, which adaptively activates/inactivates cache ways, has the potential to reduce the cache energy consumption. However, the cache activates a non-negligible number of ways to store dead blocks, which are not reused and do not contribute to performance improvement. Therefore, this paper proposes a perceptron-based cache bypassing mechanism for the way-adaptable cache to eliminate dead blocks. The evaluation results show that the proposed mechanism can reduce the cache energy consumption by up to 67%, and 14% on average.

本文言語English
ホスト出版物のタイトルIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781728117485
DOI
出版ステータスPublished - 2019 5 23
イベント22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Yokohama, Japan
継続期間: 2019 4 172019 4 19

出版物シリーズ

名前IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

Conference

Conference22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019
国/地域Japan
CityYokohama
Period19/4/1719/4/19

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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