Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis

研究成果: Conference article

1 引用 (Scopus)

抜粋

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. The parallel EGG system presented in this paper is based on a coarse-grained model of parallel processing and is implemented on a 16-node Linux PC cluster. The potential capability of parallel EGG system is demonstrated through the synthesis of a radix-4 Signed-Digit (SD) full adder circuit.

元の言語English
ページ(範囲)96-102
ページ数7
ジャーナルProceedings of The International Symposium on Multiple-Valued Logic
出版物ステータスPublished - 2002 1 1
イベント32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States
継続期間: 2002 5 152002 5 18

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

フィンガープリント Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用