This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. The parallel EGG system presented in this paper is based on a coarse-grained model of parallel processing and is implemented on a 16-node Linux PC cluster. The potential capability of parallel EGG system is demonstrated through the synthesis of a radix-4 Signed-Digit (SD) full adder circuit.
|ジャーナル||Proceedings of The International Symposium on Multiple-Valued Logic|
|出版物ステータス||Published - 2002 1 1|
|イベント||32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States|
継続期間: 2002 5 15 → 2002 5 18
ASJC Scopus subject areas
- Computer Science(all)