Optimization of the Himeno Benchmark for SX-Aurora TSUBASA

This paper focuses on optimizing the Himeno benchmark for the vector computing system SX-Aurora TSUBASA and analyzes its performance in detail. The Vector Engine (VE) of SX-Aurora TSUBASA achieves a high memory bandwidth by High Bandwidth Memory (HBM2). The Himeno benchmark solves Poisson’s equation using the Jacobi iteration method. The kernel performs 19-point stencil calculations in the 3D domain, which is known as a memory-intensive kernel. This paper introduces four optimizations in a single VE or multiple VEs for the Himeno benchmark. First, for a single VE, to exploit the high bandwidth of the last-level cache (LLC) in the VE, the highly reusable array elements are stored in the LLC with the highest priority. Second, the computational domain is decomposed by considering the architecture of the VE so that this optimization can achieve a high LLC hit ratio and a long vector length. Third, to alleviate the loop overhead that tends to be large for vector computation, loop unrolling is applied to the kernel. Fourth, for multiple VEs, the optimization to improve the sustained MPI communication bandwidth is applied. The process mapping is optimized by considering different types of communication mechanisms of SX-Aurora TSUBASA. The evaluation results show that the optimizations contribute to the long vector length, the high LLC hit ratio, and the short MPI communication time of the Himeno benchmark. As a result, the performance and the power efficiency are improved due to efficient vector processing through the optimizations.