On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis

Power noise waveforms within cryptographic VLSI circuits in a 65 nm CMOS technology are captured by using an on-chip voltage waveform monitor (OCM). The waveform measurements emphasize the correlation of dynamic voltage drops to internal logical activities during the processing of Advance Encryption Standard (AES), and resolve the physical processes in the information leakage of such as secret key bytes through Correlated Power Analysis (CPA). The time window of significant importance where the leakage most likely happens is clearly designated within a single clock cycle in the final stage of AES processing. The primary frequency components of power noise in the leakage are shown to be localized within an extremely low frequency region. The level of information leakage is strongly associated with the increase of dynamic voltage drops against increment of the Hamming distance in the AES processing. The on-chip power noise measurements unveil the facts about side-channel information leakage behind the traditional CPA with on-board sensing of power current through a resistor of 1 ohm.