On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis

Daisuke Fujimoto, Noriyuki Miura, Yu-Ichi Hayashi, Naofumi Homma, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean Luc Danger

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

Power noise waveforms within cryptographic VLSI circuits in a 65 nm CMOS technology are captured by using an on-chip voltage waveform monitor (OCM). The waveform measurements emphasize the correlation of dynamic voltage drops to internal logical activities during the processing of Advance Encryption Standard (AES), and resolve the physical processes in the information leakage of such as secret key bytes through Correlated Power Analysis (CPA). The time window of significant importance where the leakage most likely happens is clearly designated within a single clock cycle in the final stage of AES processing. The primary frequency components of power noise in the leakage are shown to be localized within an extremely low frequency region. The level of information leakage is strongly associated with the increase of dynamic voltage drops against increment of the Hamming distance in the AES processing. The on-chip power noise measurements unveil the facts about side-channel information leakage behind the traditional CPA with on-board sensing of power current through a resistor of 1 ohm.

本文言語English
ホスト出版物のタイトルProceedings of the 2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013
ページ405-410
ページ数6
出版ステータスPublished - 2013 12月 24
イベント2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013 - Brugge, Belgium
継続期間: 2013 9月 22013 9月 6

出版物シリーズ

名前IEEE International Symposium on Electromagnetic Compatibility
ISSN(印刷版)1077-4076
ISSN(電子版)2158-1118

Other

Other2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013
国/地域Belgium
CityBrugge
Period13/9/213/9/6

ASJC Scopus subject areas

  • 凝縮系物理学
  • 電子工学および電気工学

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